1. Field of the Invention
The present invention relates generally to integrated circuits and package integration and, more particularly, to the integration of radio frequency inductors in cost effective package technologies that enable efficient and high performance integrated circuit chip to package communication.
2. Description of the Related Art
Commensurate with the need for higher performing integrated circuits, there is also a need for low cost solutions due to a high demand for affordable consumer electronics. This demand is particularly evident in the cellular telephone market, where consumers are demanding more functionality, versatility, useful life, etc., while at the same time expecting cellular telephone costs to keep decreasing.
As is well known, electronics like cellular telephones utilize a combination of radio frequency (RF) circuits and digital electronics. As circuit developers push for xe2x80x9csystem-on-a-chipxe2x80x9d solutions, the RF circuitry is now being integrated into the same chip or a set of chips in order to present the consumer with a compact, light weight, and powerful electronic device. Unlike conventional digital and mixed signal integrated circuits, RF circuits need inductors in addition to transistors, resistors and capacitors. Implementing the transistors, resistors, and capacitors in a conventional integrated circuit chip is generally straight forward and efficient. However, implementing inductors on the integrated circuit chip presents a challenging proposition.
As is well known to those skilled in the art of RF circuitry, designing inductors on a chip will require a substantial amount of chip area. For ease of description, reference is now drawn to FIG. 1A, where a cross-sectional view 10 of a semiconductor substrate 12 of a chip is shown. In general, when an inductor is fabricated on a chip, other conventional transistor devices 14 will not be allowed to be designed in the substrate 12 over an on-chip inductor reserved area 16 (i.e., where only inductors will be fabricated). Typically, a single on-chip inductor will consume an area of about 400 microns by 400 microns. Although the design of a single inductor on the chip may not pose a large threat to the available chip area, most modest RF circuits generally require anywhere between 4 inductors to 16 inductors, and other more sophisticated RF circuits can require substantially more than 16 inductors. It should thus be appreciated that on-chip inductors used in RF circuits places a very large demand on chip area, which necessarily translates into larger silicon chips and greater IC chip cost.
FIG. 1B illustrates a simplified example of system circuitry 20 for use in cellular phone applications. In this example, the system circuitry 20 has antennas 22a and 22b, in which 22a can be used for receiving and 22b can be used for transmitting. Of course, a single antenna can also be used for both the receiving and transmitting tasks. From the receiving antenna 22a, the received signal is passed through a filter/impedance matching circuit 24a, a low noise amplifier (LNA) 26, and another filter/impedance matching circuit 24b. The signal is then passed to a down-converter 28a that is well suited to convert the received RF signal into a digitized signal. The digitized signal is then passed to a digital CMOS base band processor. For transmitting, the digital CMOS base band processor passes a digital signal to an up-converter 28b. The up-converter 28b will then process the digital signal into a suitable RF signal that is communicated to a power amplifier 34. Once the signal is amplified, the signal is transmitted out of the transmitting antenna 22b, or alternatively via the same antenna 22a. 
As will be apparent to one of skill in the art, upon analyzing the functionality of the system circuitry 20, up to about 16 inductors may be needed to implement the necessary RF signal processing. As a result, because inductors will continue to be needed in RF circuit applications, the size of the RF circuitry chips will unfortunately continue to take up a lot of chip area.
FIG. 1C illustrates a cross-sectional view of the substrate 12, having a patterned metallization line 40 over a dielectric layer 41. FIG. 1F shows a circuit representation of an inductor that is fabricated on a chip. In general, the inductor Lchip will have a parasitic series resistance Rchip, and a parasitic capacitance Cchip that is identified as C1 in FIG. 1C. The parasitic series resistance Rchip is identified as R1, which corresponds to the series resistance along the patterned metallization line 40. Because the resistance R1 can be substantial in certain cases, designers typically attempt to replicate the patterned metallization line 40 over various dielectric layers. This is illustrated in FIG. 1D, where two stacked patterned metallization lines 40a and 40b are interconnected using conductive vias 42. Although the parallel resistance of both lines 40a and 40b, which are illustrated as R2, may be approximately half of R1, in actuality the total resistance including R3 (R3 resistance of the conductive vias) may be only slightly less than R1 as shown in FIG. 1E. As such, multiple stacking of metal lines may not be as effective in reducing the series resistance as expected. Although the parallel resistance of both lines 40a and 40b, which are illustrated as R2, may be thought to be approximately half of R1, in actuality by including the resistance of the conductive vias (i.e., R3), the total resistance significantly increases. As such, multiple stacking of metal lines may not be as effective in reducing the series resistance as expected. As a further drawback, when this stacking of metal lines is performed in an attempt to reduce the parasitic series resistance, the parasitic capacitance C2 will actually increase because the patterned metallization line 40b will be closer to the substrate 12.
In prior art attempts to reduce the parasitic capacitance of the inductor structure, designers have etched the substrate to increase the separation between the lowest patterned metallization line and the substrate. However, etching the substrate for this purpose departs from standard semiconductor processing, and therefore, the circuit may not have long term reliability. For more discussion on substrate etching, reference may be made to a paper entitled xe2x80x9cLarge Suspended Inductors on Silicon and Their Use in a 2-m COMS RF Amplifier,xe2x80x9d by J. Y.-C. Chang, et al., IEEE Electron Device Letters, Vol. 14, No. 5, May 1993. This paper is incorporated by reference herein.
Reference is now drawn to FIG. 1G, wherein a plot of reactance vs. frequency is provided to illustrate the off-setting affect a high parasitic capacitance can have on inductance. As shown, the reactance is initially positive at lower frequencies, however, as frequency increases, capacitive coupling begins to increase thereby dragging the inductance down. At a certain frequency, referred to as xe2x80x9ca self-resonant frequency,xe2x80x9d the positive reactance of the inductor will cross the horizontal line and produce a negative reactance. The negative reactance is, in this example, a result of the increasing parasitic capacitance as frequency increases.
It should now be evident that the on-chip inductor of FIG. 1F, will not have an inductive response over the entire operating frequency. As a result, the inductor will be limited in operation to a desired inductive operating frequency range, which extends just around or after the fall toward the self-resonant frequency.
Accordingly, one manner by which an inductor""s performance is measured is by examining what the self-resonant frequency. The greater the self-resonant frequency is, the inductor will have a greater frequency range of operation. Another manner by which an inductor""s performance is measured is by its quality factor xe2x80x9cQ.xe2x80x9d Quality factor xe2x80x9cQxe2x80x9d represents how much useful energy is stored in the inductor vs. how much energy is lost in the parasitic components (e.g., Rchip and Cchip of FIG. 1F). In on-chip inductors, the quality factor is generally known and documented to be quite low, ranging between about 2 and 8. For a better understanding of the poor quality factors obtained for on-chip inductors, reference may be made to a paper entitled xe2x80x9cA Physical Model For Planar Spiral Inductors On Silicon,xe2x80x9d by C. Patrick Yue, et al., IEEE IEDM 96, 155-158 (6.5.1-6.5.4), 1996. This paper is hereby incorporated by reference. As shown in FIGS. 6-8 of C. Patrick Yue, et al., the quality factor Q at about 1 GHz only ranges between 4 and 6.5.
Optimally, it is generally desired to have as high of a quality factor Q as possible, ranging between about 50 and 100. However, due to the high parasitic capacitance and series resistance of on-chip inductors, the quality factor will rarely reach a high desirable number. In summary, on-chip inductors generally have a poor quality factor and also have an operation limiting self-resonant frequency.
In view of the foregoing, what is needed is a technique for making inductors for use in integrated circuit systems which have superior quality factors and substantially increased self-resonant frequencies, all being obtained at a zero added fabrication cost. There is also a need for high performance inductor structures for use in RF systems, which reduce chip area consumption, have superior quality factors, and increased self-resonant frequencies.
Broadly speaking, the present invention fills these needs by providing a digital and RF circuit combination that is configured to be integrated in a chip and package arrangement. In general, the chip and package arrangement is designed to have RF inductors fabricated directly on the package in a location that is well suited to directly interface with the chip being packaged to achieve improved RF circuit performance, chip area reductions, and zero added development costs. It should be appreciated that the present invention can be implemented in numerous ways, including as a process, an apparatus, a system, a device, a computer readable medium or a method. Several inventive embodiments of the present invention are described below.
In one embodiment, a digital and radio frequency (RF) circuit is disclosed. The circuit includes a package structure having a first side that has a metallization layer. The metallization layer is divided into a first part and a second part. A semiconductor die is attached to the package structure. The semiconductor die has an interconnection side that includes an array of bumps that are configured to make electrical connection to selected ones of a first plurality of metallization traces that are defined in the first part of the metallization layer of the package structure. The circuit further includes a spiral inductor trace defined in the first part of the metallization layer of the package structure, and selected ones of the array of bumps electrically interconnect the spiral inductor trace to the semiconductor die. The spiral inductor trace having a significantly improved quality factor xe2x80x9cQxe2x80x9d and an increased self-resonant frequency relative to on-chip inductors.
In another embodiment, a method of making a circuit having RF components and digital components is disclosed. The method includes: (a) identifying the RF components in the circuit; (b) identifying inductors in the RF components; (c) pattering spiral inductors in a metallization layer of a semiconductor package, such that the spiral inductors are fabricated in a first region that is designed to receive a semiconductor chip; (d) fabricating the semiconductor chip to complete the circuit having the RF components and digital components, such that the semiconductor chip does not have inductor components; and (e) coupling the semiconductor chip to the metallization layer of the semiconductor package, such that the semiconductor chip communicates with the spiral inductors that are patterned on the metallization layer of the semiconductor package.
In yet another embodiment, disclosed is a packaged semiconductor circuit for use in processing digital and RF signals. The packaged semiconductor circuit includes a package structure having a first side that includes a metallization layer. The metallization layer has a first part at about a center of the first side and a second part that surrounds the center. The circuit further includes a semiconductor die that is attached to the package structure at about the first part of the metallization layer. The semiconductor die has an interconnection side including an array of bumps that are configured to make electrical connection to selected ones of a first plurality of metallization traces that are defined in the first part of the metallization layer of the package structure. The circuit also includes a spiral inductor trace that is formed from the metallization layer of the package structure and is defined in the first part of the metallization layer. And, selected ones of the array of bumps are electrically interconnected to a first end of the spiral inductor trace and to a second end of the spiral inductor trace, such that selected ones of the array of bumps electrically interconnect the spiral inductor trace of the package structure to the semiconductor die and to selected ones of the first plurality of metallization traces. Furthermore, the spiral inductor that is part of the package structure has a significantly improved quality factor xe2x80x9cQxe2x80x9d and self-resonant frequency compared to a die fabricated inductor.
Advantageously, by fabricating the spiral inductors on the package, lower series resistances are obtained, and lower parasitic capacitances are achieved. Because the series resistance is lower and the parasitic capacitance is lower for on the package inductors, the quality factor xe2x80x9cQxe2x80x9d for on the package inductors is significantly greater than that which is common for on-chip inductors. Further yet, the on the package inductors are also configured to have a substantially higher self-resonant frequency, relative to on-chip inductors, thereby enabling high performance operation of the RF inductors at substantially higher frequencies. These and other aspects and advantages of the invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.